Local switching networks (e.g., a switching network contained within an office building) may include a switching fabric that couples end-devices via line cards. The term “switching fabric” describes a distributed switching matrix that establishes a circuit through which data may be transmitted. A switching fabric may include a stored programmable control that seeks out a suitable combination of time slots and multiplexed highways for establishing a communication circuit between end devices. Multiple highways can simultaneously exist. The term “end device” may include desktop computers, printers, routers, other networking equipment, etc.
FIG. 1 illustrates relevant portions of an exemplary local switching network 100. In FIG. 1, local switching network 100 includes a switching fabric 102 (e.g., a cross-bar switching fabric) coupled to line cards 104 through 108. Each of the line cards may be coupled to one or more end devices or other networks. FIG. 1 shows line card 104 coupled to end devices 110 through 114, line card 106 coupled to end devices 116 through 120, and line card 108 coupled to end devices 122 through 126.
Local switching network 100 shown in FIG. 1 may employ one of many different communication protocols enabling data communication between one or more end devices 110 through 126 via line cards 104 through 108 and switching fabric 102. FIG. 1 will be described with reference to a communications protocol in which end devices communicate with each other by transferring data frames. Each data frame includes one or more lines of data.
Line cards 104 through 108 are coupled to switching fabric 102 via one or more serial data links. In FIG. 1 line card 104 is coupled to switching fabric 102 via serial downlink 128 and serial up-link 130; line card 106 is coupled to switching fabric 102 via serial downlink 132 and serial up-link 134; and line card 108 is coupled to switching fabric 102 via serial downlink 136 and serial up-link 138. Each of line cards 104 through 108 is coupled to its respective end devices via a common bus. Line card 104 is coupled to end devices 110 through 114 via common bus 140; line card 106 is coupled to end devices 116 through 120 via common bus 142; and line card 108 is coupled to end devices 122 through 126 via common bus 144.
FIG. 2a illustrates components of line card 104 of FIG. 1 relevant to the discussion of the present invention. More particularly, FIG. 2a shows line card 104 having circuit 150 coupled to circuit 152 via data buses 154a and 154b. Although not shown, each of the data buses 154a and 154b includes a plurality of conductive lines or traces formed on a printed circuit board for transmitting data bit signals between circuits 150 and 152. Circuit 150 is shown coupled to end devices 110 through 114 via common bus 140. Circuit 152 is shown coupled to serial up-link 130.
In operation, circuit 150 receives frames of data lines from end devices 110 to 114 via common bus 140. Although not shown, line card 104 includes circuitry which analyzes the received data lines to determine whether they are to be routed locally to one of the end devices 110 through 114, or via switching fabric 102 to one of the end devices coupled to line cards 106 or 108. If line card 104 determines that the received frames are to be routed locally, the received frames are transmitted back to one of the end devices 110 through 114 via common bus 140. If line card 104 determines that the received frames are to be routed to one of the end devices coupled to line cards 106 or 108, then circuit 150 transmits the received frames via data buses 154a and 154b. Circuit 152 reformats the frames received from circuit 150 for subsequent transmission to fabric 102 via serial up-link 130. Circuit 152 may also add routing information to each frame or data line thereof prior to their transmission to switching fabric 102.
FIG. 2b illustrates components of circuits 150 and 152 shown in FIG. 2a that are relevant to discussion of the present invention. Circuit 150 includes a data line FIFO 160 coupled to a plurality of input/output (IO) devices 162 and a plurality of IO devices 164. For ease of illustration, FIG. 2b shows only one of the IO devices 162 and one of the IO devices 164. Circuit 152 includes a data line FIFO 170 connected to the plurality of IO devices 172 and the plurality of IO devices 174. For ease of illustration, FIG. 2b shows only one of the IO devices 172 and one of the IO devices 174.
Operational aspects of transmitting data between circuits 150 and 152 will be described with respect to FIG. 2b. In general, FIFO 160 sequentially receives data lines from one of the end devices 110 through 114. FIFO 160 temporarily stores the received data lines until they are ready to be transmitted to circuit 152. When ready, FIFO 160 outputs a data line with each transition edge (i.e., rising or falling edge) of a clock provided thereto. Equally sized upper and lower portions of each data line are simultaneously provided to IO devices 162 and IO devices 164, respectively. IO devices 162 and IO devices 164 transmit the upper and lower portions, respectively, to data buses 154a and 154b, respectively, with each transition edge of the clock signal provided thereto. Data buses 154a and 154b, in turn, transmit in parallel the upper and lower portions to IO devices 172 and IO devices 174, respectively, of circuit 152. With each transition edge of the clock or clocks provided to IO devices 172 and IO devices 174, the upper and lower portions transmitted by data buses 154a and 154b, respectively, are reassembled and stored in FIFO 170.
The operation of circuits 150 and 152 described above presumes no relative delay in the transmission of corresponding upper and lower portions of data lines between FIFOs 160 and 170. In practice, the transmission of data line portions between FIFO 160 and FIFO 170 is subject to one or more relative delays. For example, variations in temperature of components of IO devices 162 and 164, variations in power supply voltage provided to IO devices 162 and 164, or physical variations of the transistors that form IO devices 162 and 164, may result in IO devices 162 transmitting the upper portion of a data line before or after transmission of the corresponding lower portion of the data line by IO devices 164. The traces of data bus 154a on average may be longer or shorter than the average length of traces of data bus 154b such that the data bus transmission time for the upper portion of data lines may be greater or smaller than the data bus transmission time of the corresponding lower portion. The clock signal provided to IO devices 162 may be delayed with respect to the clock signal provided to IO devices 164. IO devices 172 and 174, like their counterparts 10 devices 162 and 164, are subject to variations in operating temperature and variations in the power supply provided thereto. The transistors that form IO devices 172 and 174 may differ physically. Additionally, the clock signal provided to IO devices 172 may be delayed with respect to the clock signal provided to IO devices 174. As a result of one or more of the above delay factors, IO devices 172 may gate the upper portion of a data line received via data bus 154a before or after IO devices 174 gate the corresponding lower portion received via data bus 154b. 
FIG. 2c illustrates the potential effects of relative delays in transmission of corresponding upper and lower data line portions between FIFO 160 and FIFO 170. FIG. 2c shows contents of FIFO 160 at time t=t0. More particularly, FIFO 160 stores n data lines destined to be transmitted via data buses 154a and 154b to FIFO 170. In FIFO 160, Ax and Bx represent the upper and lower portions of each data line Dx, respectively. For example, data lines A1 and B1 represent the upper and lower portions of data line D1, respectively. FIG. 2c also illustrates FIFO 170 after data lines D1 through Dn have been transmitted as described above. For purposes of explanation, it will be presumed that transmission of the upper portion of each data line between FIFO 160 and FIFO 170 is delayed with respect to the corresponding lower portion. Because of the relative delay, corresponding upper and lower data line portions are not reassembled by circuit 152 into valid data lines prior to storage in FIFO 170. FIG. 2c shows the contents of FIFO 170 after transmission of the data lines D1 through Dn. As can be seen in FIG. 2c, the data lines stored in FIFO 170 are invalid since they consist of noncorresponding upper and lower portions.